SRAM is a commonly used volatile memory device. Therefore, when the power source supplied to SRAM is shut down, the data stored in SRAM disappear. The memory cells in SRAM are used for storing data by changing the conduction state of the internal transistors in a memory cell. This is quite different from dynamic RAM (DRAM) which stores data by charging and discharging capacitors. The access speed of SRAM is very fast so it is widely applied to computer systems as cache memory.
As contemporary memories have progressed towards ever smaller process scales and lower operating voltages, it is known that it may be necessary to take steps to ensure that read stability is maintained. Read stability relates to the ability of a memory to maintain the value of a data bit held by a bit cell of the memory without change when the data bit is read. Contemporary memory may be at a level where access disturbance margin (ADM) or static noise margin (SNM) impacts read stability. Impacted read stability can, for example, result from process variation or non-optimal operating voltages.
One known technique for addressing read instability is to lower the voltage applied to the relevant wordline for at least part of the read process. By applying a lower voltage to the bit cell access gates, in particular during the early portion of the read process, the internal nodes are less disturbed and the bit cell is more stable. Various techniques are known for achieving this lowered voltage on the wordline, such as charge injection/extraction solutions, which seek to vary the wordline voltage by selectively connecting a capacitive element to the wordline, yet these known techniques are susceptible to process and temperature variation. Frequently, a transistor is connected to the wordline to pull down the wordline high logic value (“1”) voltage. To keep the wordline driving speed sufficiently high, the transistor is large and consumes a large amount of DC current.
Accordingly, it is desirable to provide an improved SRAM memory with read assist. Further, it is desirable to provide a technique that enables application of a read assist wordline voltage while utilizing a reduce current as compared to conventional techniques. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.